Memory cells of a dynamic random access memory (DRAM) generally comprise a storage capacitor for storing an electrical charge which represents an information to be stored, and an access transistor which is connected with the storage capacitor. The access transistor comprises a first and a second source/drain regions, a channel connecting the first and the second source/drain regions as well as a gate electrode controlling an electrical current flow between the first and second source/drain regions. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms part of a word line and is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out. In particular, the information is read out to a corresponding bit line via a bit line contact.
In the currently used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends in the substrate in a direction perpendicular to the substrate surface.
According to another implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
A memory device further comprises a peripheral portion. Generally, the peripheral portion of the memory device includes circuitry for addressing memory cells and for sensing and processing the signals received from the individual memory cells. Usually, the peripheral portion is formed in the same semiconductor substrate as the individual memory cells. Hence, it is highly desirable to have a manufacturing process by which the components of the memory cell array and the peripheral portion can be formed simultaneously.
Generally, a DRAM memory cell array is desired that includes a higher packaging density which can be produced by a simple, robust process having a low complexity and a high yield.
For example, U.S. Pat. No. 6,545,904 discloses a memory cell including an access transistor and a storage capacitor, which can be formed so as to implement a 6 F2 (6 F×F) DRAM array, wherein F denotes the minimum pitch according to the technology used. In particular, two neighbouring access transistors are arranged, so that they have one common bit line contact. In addition, neighbouring access transistors formed on a single active area line are electrically isolated from each other by an isolation gate line.
In addition, U.S. Pat. No. 6,419,948 discloses a memory cell array in which the active area is formed as a continuous line. The active area line and the bit line are formed as weaving lines, so that, when looked at in a plan view, one bit line and one corresponding active area line intersect at many points. According to this layout, the memory cells can have an area of about 6 F2.
DE 199 28 781 discloses a 6 F2 memory cell in which two adjacent memory cells share one common bit line contact. Two neighbouring pairs of memory cells which are assigned to one active area line are separated and electrically isolated from each other by a groove which is filled with an isolating material.
Furthermore, U.S. Pat. No. 5,502,320 discloses a memory cell array in which transistors are formed in continuous active area lines. The active area lines are arranged in parallel with the bit lines. Two adjacent pairs of neighbouring memory cells are separated and isolated from each other by applying an appropriate voltage to isolation gate lines which are arranged between the two adjacent pairs of memory cells. The word lines and the isolation gate lines are implemented as buried word lines and buried isolation gate lines, respectively.